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9db633 idt ? six output differential buffer for pcie gen3 1668c?04/20/1 1 six output differential buffer for pcie gen3 1 da t asheet recommended application:6 output pcie gen3 zero-delay/fanout buffer general description: the 9db633 zero-delay buffer supports pcie gen3 requirements, while being backwards compatible to pcie gen2 and gen1. the 9db633 is dr iv en b y a diff erential src output pair from an idt 932s421 or 932sq420 or equivalentmain cloc k gener ator . it atten uates jitter on the input cloc k and has a selectable pll bandwidth to maximizeperformance in systems with or without spread-spectrum clocking. an smbus interface allows control of the pll bandwidth and bypass options, while 2 clock request (oe#) pins make the 9db633 suitable for express card applications. key specifications: ? cycle-to-cycle jitter < 50 ps ? output-to-output skew < 50 ps ? pcie gen3 phase jitter < 1.0ps rms features/benefits:? oe# pins/suitable for express card applications ? pll or bypass mode/pll can dejitter incoming clock ? selectable pll bandwidth/minimizes jitter peaking indownstream pll's ? spread spectrum compatible/tracks spreading inputclock for low emi ? smbus interface/unused outputs can be disabled output features:? 6 - 0.7v current mode differential hcsl output pairs block diagram spread compatible pll control logic smbdat smbclk src_in src_in# pll_bw iref dif1 dif4 oe4# oe1# dif(0,2,3,5)
idt ? six output differential buffer for pcie gen3 1668c?04/20/1 1 9db633 six output differential buffer for pcie gen3 2 dat asheet po wer distrib ution t ab le pin configuration vdd gnd 7, 13, 16, 22 8,21 differential outputs 13 8 smbus n/a 27 iref 28 27 analog vdd & gnd for pll core description pin number pll_bw 1 28 vdda src _in 2 27 gnda src_in# 3 26 iref voe1# 4 25 voe4# d if_0 5 24 dif_5 dif_0# 6 23 dif_5# vdd 7 22 vdd gnd 8 21 gnd d if_1 9 20 dif_4 dif_1# 10 19 dif_4# d if_2 11 18 dif_3 dif_2# 12 17 dif_3# vdd 13 16 vdd smbdat 14 15 smbclk 9db633 120k ohm pull down resistors note: pins preceeded by ' v ' have internal
idt ? six output differential buffer for pcie gen3 1668c?04/20/1 1 9db633 six output differential buffer for pcie gen3 3 dat asheet pin description pin # pin name pin type description 1 pll_bw in 3.3v input for selecting pll band width 0 = low, 1= high 2 src_in in 0.7 v differential src true input 3 src_in# in 0.7 v differential src complementary inpu t 4 voe1# in active low input for enabling dif pair 1. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 5 dif_0 out 0.7v differential true clock output 6 dif_0# out 0.7v differential complementary clock output 7 vdd pwr power supply, nominal 3.3v 8 gnd in ground pin. 9 dif_1 out 0.7v differential true clock output 10 dif_1# out 0.7v differential complementary clock ou tput 11 dif_2 out 0.7v differential true clock output 12 dif_2# out 0.7v differential complementary clock output 13 vdd pwr power supply, nominal 3.3v 14 smbdat i/o data pin of smbus circuitry, 5v tolerant 15 smbclk in clock pin of smbus circuitry, 5v tolerant 16 vdd pwr power supply, nominal 3.3v 17 dif_3# out 0.7v differential complementary clock output 18 dif_3 out 0.7v differential true clock output 19 dif_4# out 0.7v differential complementary clock output 20 dif_4 out 0.7v differential true clock output 21 gnd pwr ground pin. 22 vdd pwr power supply, nominal 3.3v 23 dif_5# out 0.7v differential complementary clock ou tput 24 dif_5 out 0.7v differential true clock output 25 voe4# in active low input for enabling dif pair 4. this pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs 26 iref out this pin establishes the reference for the differen tial current-mode output pairs. it requires a fixed precision resistor to ground. 475o hm is the standard value for 100ohm differential impedance. other impedances req uire different v alues. see data sheet. 27 gnda pwr ground pin for the pll core. 28 vdda pwr 3.3v power for the pll core. note: pins preceeded by ' v ' have internal 120k ohm pull down resistors
idt ? six output differential buffer for pcie gen3 1668c?04/20/1 1 9db633 six output differential buffer for pcie gen3 4 dat asheet electrical characteristics - absolute maximum ratin gs parameter symbol conditions min typ max units notes 3.3v core supply voltage vdda 4.6 v 1,2 3.3v logic supply voltage vdd 4.6 v 1,2 input low voltage v il gnd-0.5 v 1 input high voltage v ih except for smbus interface v dd +0.5v v 1 input high voltage v ihsmb smbus clock and data pins 5.5v v 1 storage temperature ts -65 150 c 1 junction temperature tj 125 c 1 input esd protection esd prot human body model 2000 v 1 1 guaranteed by design and characterization, not 100% tested in production. 2 operation under these conditions is neither implied nor guaranteed. electrical characteristics - input/supply/common pa rameters ta = t com or t ind; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes t com commmercial range 0 70 c 1 t ind industrial range -40 85 c 1 input high voltage v ih single-ended inputs, except smbus, low threshold and tri-level inputs 2 v dd + 0.3 v 1 input low voltage v il single-ended inputs, except smbus, low threshold and tri-level inputs gnd - 0.3 0.8 v 1 i in single-ended inputs, v in = gnd, v in = vdd -5 5 ua 1 i inp single-ended inputs v in = 0 v; inputs with internal pull-up resistors v in = vdd; inputs with internal pull-down resistors -200 200 ua 1 f ibyp v dd = 3.3 v, bypass mode 10 110 mhz 2 f ipll v dd = 3.3 v, 100mhz pll mode 33 100.00 110 mhz 2 pin inductance l pin 7 nh 1 c in logic inputs, except dif_in 1.5 5 pf 1 c indif_in dif_in differential clock inputs 1.5 2.7 pf 1,4 c out output pin capacitance 6 pf 1 clk stabilization t stab from v dd power-up and after input clock stabilization or de-assertion of pd# to 1st clock 1.8 ms 1,2 input ss modulation frequency f modin allowable frequency (triangular modulation) 30 33 khz 1 oe# latency t latoe# dif start after oe# assertion dif stop after oe# deassertion 1 3 cycles 1,3 tdrive_pd# t drvpd dif output enable after pd# de-assertion 300 us 1,3 tfall t f fall time of control inputs 5 ns 1,2 trise t r rise time of control inputs 5 ns 1,2 smbus input low voltage v ilsmb 0.8 v 1 smbus input high voltage v ihsmb 2.1 v ddsmb v 1 smbus output low voltage v olsmb @ i pullup 0.4 v 1 smbus sink current i pullup @ v ol 4 ma 1 nominal bus voltage v ddsmb 3v to 5v +/- 10% 2.7 5.5 v 1 sclk/sdata rise time t rsmb (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata fall time t fsmb (min vih + 0.15) to (max vil - 0.15) 300 ns 1 smbus operating frequency f maxsmb maximum smbus operating frequency 100 khz 1,5 1 guaranteed by design and characterization, not 100% tested in production. 2 control input must be monotonic from 20% to 80% of input swing. 5 the differential input clock must be running for th e smbus to be active ambient operating temperature input current 3 time from deassertion until outputs are >200 mv 4 dif_in input capacitance input frequency
idt ? six output differential buffer for pcie gen3 1668c?04/20/1 1 9db633 six output differential buffer for pcie gen3 5 dat asheet electrical characteristics - clock input parameters ta = t com or t ind; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes input high voltage - dif_in v ihdif differential inputs (single-ended measurement) 600 800 1150 mv 1 input low voltage - dif_in v ildif differential inputs (single-ended measurement) v ss - 300 0 300 mv 1 input common mode voltage - dif_in v com common mode input voltage 300 1000 mv 1 input amplitude - dif_in v swing peak to peak value 300 1450 mv 1 input slew rate - dif_in dv/dt measured differentially 0.4 8 v/ns 1,2 input leakage current i in v in = v dd , v in = gnd -5 5 ua 1 input duty cycle d tin measurement from differential wavefrom 45 55 % 1 input jitter - cycle to cycle j difin differential measurement 0 125 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured through +/-75mv window centered around differential zero electrical characteristics - dif 0.7v current mode differential outputs t a = t com or t ind; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes slew rate trf scope averaging on 0.6 2.5 4 v/ns 1, 2, 3 slew rate matching ? trf slew rate matching, scope averaging on 9.5 20 % 1, 2, 4 voltage high vhigh 660 740 850 1 voltage low vlow -150 8 150 1 max voltage vmax 760 1150 1 min voltage vmin -300 -3 1 vswing vswing scope averaging off 300 1506 mv 1, 2 crossing voltage (abs) vcross_abs scope averaging off 250 378 550 mv 1, 5 crossing voltage (var) ? -vcross scope averaging off 54 140 mv 1, 6 2 measured from differential waveform 6 the total variation of all vcross measurements in any particular system. note that this is a subset o f v_cross_min/max (v_cross absolute) allowed. the intent is to limit vcross induced modu lation by setting v_cross_delta to be smaller than v_cross absolute. mv statistical measurement on single-ended signal using oscilloscope math function. (scope averaging on) measurement on single ended signal using absolute value. (scope averaging off) mv 1 guaranteed by design and characterization, not 100% tested in production. iref = vdd/(3xr r ). for r r = 475 (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 (100 differential impedance). 3 slew rate is measured through the vswing voltage ra nge centered around differential 0v. this results in a +/-150mv window around differential 0v. 4 matching applies to rising edge rate for clock and falling edge rate for clock#. it is measured using a +/-75mv window centered on the average cross point where clock rising meets clock# falling. the median cross point is used to calcula te the voltage thresholds the oscilloscope is to use for the edge rate calculatio ns. 5 vcross is defined as voltage where clock = clock# measured on a component test board and only applies to the differential rising edge (i.e. clock rising and clock# falling). electrical characteristics - current consumption ta = t com or t ind; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes operating supply current i dd3.3op all outputs active @100mhz, c l = full load; 134 150 ma 1 i dd3.3pd all diff pairs driven n/a ma 1 i dd3.3pdz all differential pairs tri-stated n/a ma 1 1 guaranteed by design and characterization, not 100% tested in production. powerdown current
idt ? six output differential buffer for pcie gen3 1668c?04/20/1 1 9db633 six output differential buffer for pcie gen3 6 dat asheet electrical characteristics - output duty cycle, jit ter, skew and pll characterisitics ta = t com or t ind; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes -3db point in high bw mode 2 2.3 4 mhz 1 -3db point in low bw mode 0.4 0.5 1 mhz 1 pll jitter peaking t jpeak peak pass band gain 1 2 db 1 duty cycle t dc measured differentially, pll mode 45 48 55 % 1 duty cycle distortion t dcd measured differentially, bypass mode @100mhz -2 1 2 % 1, 4 t pdbyp bypass mode, v t = 50% 2500 3660 4500 ps 1 t pdpll hi bw pll mode v t = 50% -250 0 250 ps 1 skew, output to output t sk3 v t = 50% 15 50 ps 1 pll mode 40 50 ps 1,3 additive jitter in bypass mode 10 50 ps 1,3 1 guaranteed by design and characterization, not 100% tested in production. 2 i ref = v dd /(3xr r ). for r r = 475 (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 . 3 measured from differential waveform 4 duty cycle distortion is the difference in duty cy cle between the output and the input clock when the device is operated in bypass mode. skew, input to output jitter, cycle to cycle t jcyc-cyc pll bandwidth bw electrical characteristics - pcie phase jitter para meters ta = t com or t ind; supply voltage vdd = 3.3 v +/-5% parameter symbol conditions min typ max units notes t jphpcieg1 pcie gen 1 32 86 ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz 1.1 3 ps (rms) 1,2 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 2.3 3.1 ps (rms) 1,2 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 0.5 1 ps (rms) 1,2,4 t jphpcieg1 pcie gen 1 2 5 ps (p-p) 1,2,3 pcie gen 2 lo band 10khz < f < 1.5mhz 0.2 0.3 ps (rms) 1,2 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 0.8 1 ps (rms) 1,2 t jphpcieg3 pcie gen 3 (pll bw of 2-4mhz, cdr = 10mhz) 0.1 0.2 ps (rms) 1,2,4 1 applies to all outputs. 3 sample size of at least 100k cycles. this figures extrapolates to 108ps pk-pk @ 1m cycles for a ber of 1-12. 4 subject to final radification by pci sig. t jphpcieg2 2 see http://www.pcisig.com for complete specs t jphpcieg2 phase jitter, pll mode additive phase jitter, bypass mode
idt ? six output differential buffer for pcie gen3 1668c?04/20/1 1 9db633 six output differential buffer for pcie gen3 7 dat asheet hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express add-in board ref_clk input figure 2: pci express connector routing common recommendations for differential routing dime nsion or value unit figure l1 length, route as non-coupled 50ohm trace 0.5 max i nch 1 l2 length, route as non-coupled 50ohm trace 0.2 max i nch 1 l3 length, route as non-coupled 50ohm trace 0.2 max i nch 1 rs 33 ohm 1 rt 49.9 ohm 1 down device differential routing l4 length, route as coupled microstrip 100ohm diffe rential trace 2 min to 16 max inch 1 l4 length, route as coupled stripline 100ohm differ ential trace 1.8 min to 14.4 max inch 1 differential routing to pci express connector l4 length, route as coupled microstrip 100ohm diffe rential trace 0.25 to 14 max inch 2 l4 length, route as coupled stripline 100ohm differ ential trace 0.225 min to 12.6 max inch 2 src reference clock hcsl output buffer l1 l1' rs l2 l2' rs l4' l4 l3 l3' rt rt pci express down device ref_clk input figure 1: down device routing
idt ? six output differential buffer for pcie gen3 1668c?04/20/1 1 9db633 six output differential buffer for pcie gen3 8 dat asheet vdiff vp-p vcm r1 r2 r3 r4 note 0.45v 0.22v 1.08 33 150 100 100 0.58 0.28 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ics874003i-02 input compati ble 0.60 0.3 1.2 33 174 140 100 standard lvds r1a = r1b = r1 r2a = r2b = r2 alternative termination for lvds and other common d ifferential signals (figure 3) hcsl output buffer l1 l1' r1b l2 l2' r1a l4' l4 l3 r2a r2b down device ref_clk input figure 3 l3' r3 r4 component value note r5a, r5b 8.2k 5% r6a, r6b 1k 5% cc 0.1 f vcm 0.350 volts cable connected ac coupled application (figure 4) pcie device ref_clk input figure 4 r5a l4' l4 3.3 volts r5b r6a r6b cc cc
idt ? six output differential buffer for pcie gen3 1668c?04/20/1 1 9db633 six output differential buffer for pcie gen3 9 dat asheet general smbus serial interface information for the 9db633 ho w to write: ? controller (host) sends a star t bit. ? controller (host) sends the write address d4 (h) ? ics clock will acknowledge ? controller (host) sends the begining byte location = n ? ics clock will acknowledge ? controller (host) sends the data byte count = x ? ics clock will acknowledge ? controller (host) star ts sending byte n thr ough byte n + x -1(see note 2) ? ics clock will acknowledge each byte one at a time ? controller (host) sends a stop bit how to read:? controller (host) will send star t bit. ? controller (host) sends the write address d4 (h) ? ics clock will acknowledge ? controller (host) sends the begining bytelocation = n ? ics clock will acknowledge ? controller (host) will send a separ ate star t bit. ? controller (host) sends the read address d5 (h) ? ics clock will acknowledge ? ics clock will send the data byte count = x ? ics clock sends byte n + x -1 ? ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . ? controller (host) will need to acknowledge each byte ? controllor (host) will send a not acknowledge bit ? controller (host) will send a stop bit ics (sla ve /re ce ive r) t w r ack ack ack ack ack p byte n + x - 1 data byte count = x beginning byte n stop bit x byte index block write operation slave address d4 (h ) beginning byte = n w rite start bit controlle r (host) t start bit w r w rite rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge p stop bit ics (sla ve /re ce ive r) controlle r (host) x byte ack ack data byte count = x ack slave address d3 (h ) index block read operation slave address d4 (h ) beginning byte = n ack ack
idt ? six output differential buffer for pcie gen3 1668c?04/20/1 1 9db633 six output differential buffer for pcie gen3 10 dat asheet smb ustable: device control register, read /write add ress (d4/d5) pin # name control function type 0 1 default bit 7 sw_en enables smbus control of bits (1:0) rw pll controlled by smbus registers pll controlled by device pins 1 bit 6 rw x bit 5 rw x bit 4 rw x bit 3 rw x bit 2 rw x bit 1 pll bw #adjust selects pll bandwidth rw low bw high bw 1 bit 0 pll enable bypasses pll for board test rw pll bypassed (fan out mode) pll enabled (zdb mode) 1 smb ustable: output enable register pin # name control function type 0 1 default bit 7 rw x bit 6 rw x bit 5 pciex5 output control rw disable enable 1 bit 4 rw x bit 3 pciex3 output control rw disable enable 1 bit 2 pciex2 output control rw disable enable 1 bit 1 rw x bit 0 pciex0 output control rw disable enable 1 smb ustable: function select register pin # name control function type 0 1 default bit 7 rw x bit 6 rw x bit 5 rw x bit 4 rw x bit 3 rw x bit 2 rw x bit 1 rw x bit 0 rw x smb ustable: vendor & revision id register pin # name control function type 0 1 default bit 7 rid3 r - - 0 bit 6 rid2 r - - 0 bit 5 rid1 r - - 0 bit 4 rid0 r - - 1 bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 - reserved - reserved - reserved - vendor id -- - - -- - - -- - - - - - byte 3 reserved - 18,17 11,12 - 5,6 byte 2 -- reserved - -- byte 1 -- 24,23 - reserved - - reserved - - reserved - reserved - reserved revision id - reserved byte 0 - - reserved - reserved reserved - reserved -- reserved - reserved
idt ? six output differential buffer for pcie gen3 1668c?04/20/1 1 9db633 six output differential buffer for pcie gen3 11 dat asheet smbustable: device id pin # name control function type 0 1 default bit 7 r 0 bit 6 r 0 bit 5 r 0 bit 4 r 0 bit 3 r 0 bit 2 r 1 bit 1 r 1 bit 0 r 0 smbustable: byte count register pin # name control function type 0 1 default bit 7 bc7 rw - - 0 bit 6 bc6 rw - - 0 bit 5 bc5 rw - - 0 bit 4 bc4 rw - - 0 bit 3 bc3 rw - - 0 bit 2 bc2 rw - - 1 bit 1 bc1 rw - - 1 bit 0 bc0 rw - - 0 device id = 06 hex - -- - - byte 4 -- - byte 5 - writing to this register will configure how many bytes will be read back, default is 06 = 6 bytes. -- - - - - - - -- - - - --
idt ? six output differential buffer for pcie gen3 1668c?04/20/1 1 9db633 six output differential buffer for pcie gen3 12 dat asheet 28-pin ssop package drawing and dimensions 209 mil ssop min max min max a -- 2.00 -- .079 a1 0.05 -- .002 -- a2 1.65 1.85 .065 .073 b 0.22 0.38 .009 .015 c 0.09 0.25 .0035 .010 d e 7.40 8.20 .291 .323 e1 5.00 5.60 .197 .220 e l 0.55 0.95 .022 .037 n 0 8 0 8 variations min max min max 28 9.90 10.50 .390 .413 10-0033 reference doc.: jedec publication 95, mo-150 0.0256 basic common dimensions in millimeters in inches common dimensions 209 mil ssop n see variations see variations d mm. d (inch) symbol see variations see variations 0.65 basic
idt ? six output differential buffer for pcie gen3 1668c?04/20/1 1 9db633 six output differential buffer for pcie gen3 13 dat asheet 28-pin tssop package drawing and dimensions indexarea 1 2 n d e1 e a seating plane a1 a a2 e - c - b c l aaa c min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.19 0.30 .007 .012 c 0.09 0.20 .0035 .008 de e1 4.30 4.50 .169 .177 e l 0.45 0.75 .018 .030 n 0 8 0 8 aaa -- 0.10 -- .004 variations min max min max 28 9.60 9.80 .378 .386 10-0035 see variations see variations 0.65 basic reference doc.: jedec publication 95, mo-153 n see variations see variations d mm. d (inch) 4.40 mm. body, 0.65 mm. pitch tssop 6.40 basic 0.252 basic 0.0256 basic common dimensions in millimeters in inches common dimensions (173 mil) (25.6 mil) symbol ordering information part / order number shipping packaging package tempera ture 9db633aflf tubes 28-pin ssop 0 to +70c 9db633aflft tape and reel 28-pin ssop 0 to +70c 9DB633AFILF tubes 28-pin ssop -40 to +85c 9db633aflift tape and reel 28-pin ssop -40 to +85c 9db633aglf tubes 28-pin tssop 0 to +70c 9db633aglft tape and reel 28-pin tssop 0 to +70c 9db633agilf tubes 28-pin tssop -40 to +85c 9db633agilft tape and reel 28-pin tssop -40 to +85c "lf" after the package code are the pb-free configu ration and are rohs compliant. "a" is the device revision designator (will not cor relate to the datasheet revision).
9db633 six output differential buffer for pcie gen3 14 dat asheet innovate with idt and accelerate your future networks. cont act: www .idt .com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for t ech support 408-284-6578 pcclockhelp@id t.com corporate headquarters integrated device t echnology , inc. 6024 silver creek v alley road san jose, ca 95138 united s t ates 800 345 7015 +408 284 8200 (out side u.s.) asia pacific and japan idt singapore pte. ltd. 1 kallang sector #07-01/06 kolamayer industrial park singapore 349276 phone: 65-6-744-3356 fax: 65-6-744-1764 europe idt europe limited 321 kingston road leatherhead, surrey kt22 7tu england phone: 44-1372-363339 fax: 44-1372-378851 ? 2010 integrated device t echnology , inc. all right s reserved. product specifications subject to change without notice. idt , ics, and the idt logo are trademarks of integrated device t echnology , inc. accelerated thinking is a service mark of integrated device t echnology , inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa ?? revision history rev. originator issue date description page # a rdw 6/30/2010 released to final b rdw 7/12/2010 changed "pwd" to "default" in smbus re gister descriptions 10,11 c rdw 4/20/2011 changed pull down indicator from '**' to 'v'.

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